1. Field of the Invention
The present invention relates generally to an electrical power regulator, and more particularly to a power regulator having an adjustable feedback loop, to an adjustable feedback loop for a power regulator, and to a method for adjusting a feedback loop of a power regulator.
2. Description of the Related Art
Power regulators are used in many electrical devices to provide controlled power to the circuits in the device. The power regulators may be used to translate the voltage to a desired level, to regulate the power to a particular output level, or the like. Power regulators are configured according to several different designs. One such design is a switching power regulator, where an input voltage is switched on and off rapidly and then is smoothed to provide an output voltage at a lower level. Regulators generally use a feedback control loop that in many configurations includes an error amplifier to compare the output voltage of the regulator with a reference value to maintain tight control of the output.
A power regulator 80 is shown generally in FIG. 8a, including an input 82, a power conversion stage 84, and an output 86. The power conversion stage 84 has an output that is fed through a feedback network 88 to an error amplifier 90 that in turn feeds a controller 92 which controls the power conversion stage 84.
One of the critical parameters in developing a power regulator is transient response, most commonly defined as the deviation in output voltage due to a change in the load current. Another way to look at transient response is as the time that it takes the regulator to return the output voltage to a steady-state condition after a load change. Three variables that affect transient response are: 1) Cout—the amount of output capacitance, 2) fC—the overall regulator 0 dB feedback loop crossover frequency, and 3) PM—the phase margin at the crossover frequency fC.
The output capacitance Cout determines how far the output voltage moves (dV) until the regulator feedback responds to the deviation. The crossover frequency fC determines the time that it takes for the regulator to responds to the deviation. The phase margin PM is a measure of the damping of the response to the deviation. As an example, a switching power regulator with a switching frequency fsw of 350 kHz may be designed with 100 μF of output capacitance Cout and a crossover frequency fC of 60 kHz with a phase margin PM of 45° in order to achieve a critically damped response to a 50% load current step of 100 mV with a recovery time of 75 μs.
For some loads, and especially for forthcoming DSPs (Digital Signal Processors), μPs (microprocessors), ASICs (Application-Specific Integrated Circuits), and FPGAs (Field Programmable Gate-Arrays), this level of transient deviation may be too high. A typical core voltage for a DSP (digital signal processor) may be 1.2V, with an allowable cumulative deviation of only ±3%, which equates to only a 36 mV transient deviation.
In order to achieve such a small transient response, it is necessary to provide many additional output capacitors which provide additional hold-up time until the regulator feedback loop can respond. This technique may require thousands of μF (microfarads) of capacitance. These additional capacitors are generally populated on the circuit board(s) of the device.
However, applying these additional capacitors to the output has four drawbacks. The first two are simple. First, adding the extra capacitors takes up a lot of space on the printed circuit board (PCB). Second, the extra capacitors add a lot of cost to the overall BOM (Bill of Materials) for building such as device.
The third and fourth drawbacks have to do with the inter-relatedness of the crossover frequency fC and the phase margin PM to the output capacitance Cout. For a given design, adding additional capacitance results in, thirdly, a lower crossover frequency fC (slowing the response time of the regulator), and fourthly, a high likelihood of lowered phase margin PM (causing unstable operation).
Because of the third drawback, as a builder of such a device progressively adds output capacitors, there is only a small reduction in transient amplitude. The benefit of a lower voltage change over time dV/dt is counteracted by the slower response time due to a decreased crossover frequency fC.
An example of this effect is apparent from FIGS. 1a, 1b and 1c and the graph of FIG. 2. In FIG. 1a, an example of a power conversion stage of a power regulator is shown schematically, including an inductor 20 and a branch to ground having a capacitor 22 and a resistor 24. The resistor represents the intrinsic ESR (Equivalent Series Resistance) of the capacitor. The capacitor 22 here is 100 μF and the resistor is 5 milliohm. The capacitance has been increased in FIG. 1b by the addition of a branch having a capacitor 26 of 940 μF and an ESR resistance of 3 milliohm. A further increase in capacitance is provided in FIG. 1c, wherein the second branch has a 6000 μF capacitor 30 and a 1.5 milliohm ESR resistance 32. FIGS. 1b and 1c represent additional capacitance provided by the user to the power conversion stage of FIG. 1a. 
The frequency response of the power conversion stage of the power regulator is shown in FIGS. 2 and 3. In particular, in a graph 34 of gain over frequency, the gain of the regulator is graphed for different output capacitances. The crossover frequency is indicated for each graph as the zero crossing point. The crossover frequency for the circuit of FIG. 1a is shown at 36, the crossover frequency for the circuit of FIG. 1b is shown at 38, and the crossover frequency for the circuit of FIG. 1c is shown at 40. Thus, the crossover frequency fC decreases with increasing output capacitance Cout.
Because of the fourth drawback, as a builder progressively adds output capacitors, there is an increasing likelihood of instability. Adding output capacitors lowers the double-pole LC resonant frequency/phase transition frequency, which fixed feedback networks have decreasing ability to compensate for.
FIG. 3 illustrates the phase change with increases in the output capacitance. In particular, the graph 42 of phase over frequency shows the power conversion stage phase for each of the circuits of FIGS. 1a, 1b and 1c. In particular, the phase transition frequency for the circuit of FIG. 1a is shown at 44, for the circuit of FIG. 1b at 46 and for the circuit of FIG. 1c at 48. The phase transition frequency decreases with increasing output capacitance Cout.